1. Field of the Invention
The present invention relates to a clock distribution circuit, a semiconductor integrated circuit, and a clock distribution method.
2. Description of Related Art
Up to now, a batch driving system, a clock tree system, or a combination thereof has been employed in clock distribution circuits. In the clock distribution circuit of the batch driving system, a clock buffer is series-connected with a flip-flop or the like, and clocks are input. In the batch driving system, a line close to an output of the clock buffer on an integrated circuit is generally set wide to reduce a delay or improve a reliability of electromigration. In contrast, in the clock tree system, clock buffers are configured into a tree shape, and distributed on an integrated circuit. The clock distribution circuit of the clock tree system is disclosed in Japanese Unexamined Patent Application Publication No. 2001-319975.
Important factors of the clock distribution circuit are a clock skew that influences setting a chip clock timing design and a delay that influences an inter-chip clock timing design. How to reduce the skew and delay is an important problem. In the clock tree system, the skew can be more readily adjusted than the batch driving system can, and it is easy to design a circuit of this system as an integrated circuit. Hence, ASICs (Application Specific Integrated Circuit) have mainly employed the clock tree system. FIG. 4 shows an example of a clock distribution circuit for improving a clock timing accuracy, for example, suppressing such delay or variations in skew.
As shown in FIG. 4, in a conventional clock distribution circuit 900, a clock mask 911 is connected to the root where a clock is input, and a clock buffer 912 is connected to the clock mask 911. Parallel-connected clock buffers 914 and 915 are connected between the clock buffer 912 and a functional block 913. Similar clock tree structure is obtained by a clock mask 921, . . . , clock buffers 922 to 925, . . . . The clock masks 911, 921, . . . each receive a control signal mskb00 or mskb01 for determining whether or not to cancel masking.
As shown in FIG. 5, the control signal mskb00 is input to the clock mask 911 on the falling edge of the clock clkin at time t1. The clock mask 911 is turned ON in response to the control signal mskb01 to drive the clock buffer 912. The clock buffer 912 accordingly outputs the clock clkm to drive the clock buffers 914 and 915. The driven clock buffers 914 and 915 send a clock clkout to the functional block 913.
In the clock distribution circuit 900, a clock is masked at any portion of branches on the root side in the clock tree structure of, for example, the clock masks 911, 921, . . . . As a result, a current amount is largely changed when the clock masks 911, 921, . . . are turned ON/OFF. Thus, it is necessary to design an external power supply to handle a rush current when the clock masks 911, 921, . . . are turned ON/OFF.
As described above, the conventional clock distribution circuit has a problem in that a clock is masked at any portion of the root and the power supply circuit is complicated and upsized.